Yield models may be applied to increase the yield learning rate in semiconductor manufacture. Detailed equipment models can be used to predict the defect-limited yield from estimates of particles added per wafer pass. These general yield models may be refined to reflect specific processes, equipment, and design rules in more accurate critical area estimates. After validation, refined models can be applied to direct particle reduction and yield improvement efforts amid conflicting priorities. Yield improvements have been demonstrated by applying defect-limited yield models in a production manufacturing facility.
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